détails d'emploi
Are you a FPGA Design Engineer looking for a new opportunity?
Are you looking for a new contract in the Ottawa area?
We are pleased to offer you a new contract opportunity for you to consider working with an enterprise client!
- Start: ASAP
- Estimated length: 6 months
- Location: Ottawa
...
- Hybrid role (must be able to work out of the Kanata office, approx. 3 days per week)
Advantages
The telecommunications industry is currently shifting from closed, proprietary systems to Open RAN (O-RAN) architecture.
The Benefit: By working on O-RAN and eCPRI protocols, you are positioning yourself at the forefront of how future networks are built. This is "future-proof" knowledge that will be in high demand for the next decade as global carriers upgrade their infrastructure.
Responsibilities
To make these responsibilities more actionable for a job posting or a candidate brief, I’ve categorized them into three core pillars: Strategic Leadership, Technical Execution, and System Architecture.
Here is a streamlined, professional rewrite of the responsibilities:
1. System Architecture & Innovation
Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
2. Technical Implementation & Validation
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
3. Leadership & Consultative Strategy
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing "whiteboard-level" solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.
Competitive Intelligence: Conduct technical evaluations and competitive analyses to ensure the product remains a leader in the wireless infrastructure market.
Qualifications
1. FPGA Development & Tools
7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
2. Networking & Connectivity (High Priority)
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
3. 4G/5G Radio Domain Knowledge
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
4. Verification & Workflow
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure "first-time-right" silicon/FPGA bitstreams.
Modern Version Control: High proficiency in Git/GitHub workflows for collaborative RTL development and continuous integration.
Professional & Soft Skills
Architectural Vision: Ability to take a system-level concept and decompose it into high-performance FPGA subsystems.
Technical Leadership: Demonstrated experience mentoring junior designers and leading technical "whiteboard" architectural reviews.
Strategic Thinking: Capability to analyze competitive landscape and industry trends to influence component selection and product cost-reduction strategies.
Summary
Do you have this experience? If you answer YES, then please apply IMMEDIATELY to so we can then discuss your experience and interest in this opportunity!
Randstad Canada is committed to fostering a workforce reflective of all peoples of Canada. As a result, we are committed to developing and implementing strategies to increase the equity, diversity and inclusion within the workplace by examining our internal policies, practices, and systems throughout the entire lifecycle of our workforce, including its recruitment, retention and advancement for all employees. In addition to our deep commitment to respecting human rights, we are dedicated to positive actions to affect change to ensure everyone has full participation in the workforce free from any barriers, systemic or otherwise, especially equity-seeking groups who are usually underrepresented in Canada's workforce, including those who identify as women or non-binary/gender non-conforming; Indigenous or Aboriginal Peoples; persons with disabilities (visible or invisible) and; members of visible minorities, racialized groups and the LGBTQ2+ community.
Randstad Canada is committed to creating and maintaining an inclusive and accessible workplace for all its candidates and employees by supporting their accessibility and accommodation needs throughout the employment lifecycle. We ask that all job applications please identify any accommodation requirements by sending an email to accessibility@randstad.ca to ensure their ability to fully participate in the interview process.
This posting is for existing and upcoming vacancies.
voir plus
Are you a FPGA Design Engineer looking for a new opportunity?
Are you looking for a new contract in the Ottawa area?
We are pleased to offer you a new contract opportunity for you to consider working with an enterprise client!
- Start: ASAP
- Estimated length: 6 months
- Location: Ottawa
- Hybrid role (must be able to work out of the Kanata office, approx. 3 days per week)
Advantages
The telecommunications industry is currently shifting from closed, proprietary systems to Open RAN (O-RAN) architecture.
The Benefit: By working on O-RAN and eCPRI protocols, you are positioning yourself at the forefront of how future networks are built. This is "future-proof" knowledge that will be in high demand for the next decade as global carriers upgrade their infrastructure.
Responsibilities
To make these responsibilities more actionable for a job posting or a candidate brief, I’ve categorized them into three core pillars: Strategic Leadership, Technical Execution, and System Architecture.
Here is a streamlined, professional rewrite of the responsibilities:
1. System Architecture & Innovation
...
Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
2. Technical Implementation & Validation
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
3. Leadership & Consultative Strategy
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing "whiteboard-level" solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.
Competitive Intelligence: Conduct technical evaluations and competitive analyses to ensure the product remains a leader in the wireless infrastructure market.
Qualifications
1. FPGA Development & Tools
7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
2. Networking & Connectivity (High Priority)
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
3. 4G/5G Radio Domain Knowledge
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
4. Verification & Workflow
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure "first-time-right" silicon/FPGA bitstreams.
Modern Version Control: High proficiency in Git/GitHub workflows for collaborative RTL development and continuous integration.
Professional & Soft Skills
Architectural Vision: Ability to take a system-level concept and decompose it into high-performance FPGA subsystems.
Technical Leadership: Demonstrated experience mentoring junior designers and leading technical "whiteboard" architectural reviews.
Strategic Thinking: Capability to analyze competitive landscape and industry trends to influence component selection and product cost-reduction strategies.
Summary
Do you have this experience? If you answer YES, then please apply IMMEDIATELY to so we can then discuss your experience and interest in this opportunity!
Randstad Canada is committed to fostering a workforce reflective of all peoples of Canada. As a result, we are committed to developing and implementing strategies to increase the equity, diversity and inclusion within the workplace by examining our internal policies, practices, and systems throughout the entire lifecycle of our workforce, including its recruitment, retention and advancement for all employees. In addition to our deep commitment to respecting human rights, we are dedicated to positive actions to affect change to ensure everyone has full participation in the workforce free from any barriers, systemic or otherwise, especially equity-seeking groups who are usually underrepresented in Canada's workforce, including those who identify as women or non-binary/gender non-conforming; Indigenous or Aboriginal Peoples; persons with disabilities (visible or invisible) and; members of visible minorities, racialized groups and the LGBTQ2+ community.
Randstad Canada is committed to creating and maintaining an inclusive and accessible workplace for all its candidates and employees by supporting their accessibility and accommodation needs throughout the employment lifecycle. We ask that all job applications please identify any accommodation requirements by sending an email to accessibility@randstad.ca to ensure their ability to fully participate in the interview process.
This posting is for existing and upcoming vacancies.
voir pluspartager l'offre d'emploi
